In the rapidly advancing semiconductor manufacturing industry, complementary metal oxide semiconductor (CMOS) FinFET devices may be used in many logic and other applications and are integrated into various different types of semiconductor devices. FinFET devices typically include semiconductor fins with high aspect ratios in which the channel and source/drain regions for the transistor are formed. A gate is formed over and along the sides of the portion of the fin devices utilizing the advantage of the increased surface area of the channel and source/drain regions to produce faster, more reliable and better-controlled semiconductor transistor devices. Further advantages of FinFETs include reducing the short channel effect and higher current flow.
Current FinFET technology has challenges however. For example, ion implantation is typically used to form a lightly doped drain (LDD) region. Ion implantation creates a non-conformal doping profile of the fin (for example, heavier doping at the top of the fin than the bottom of the fin, which is found closer to the substrate). This non-conformal doping profile may create issues including those associated non-uniform device turn on. By using a tilt implant, the photo resist height induced shadowing effects and pre amorphization (PAI) induced twin boundary defects will be disadvantageous.
As such, an improved fabrication method for a FinFET element is desired.